The present invention pertains to secure telecommunications and more particularly to a cryptographic logic arrangement for providing terminal-to-terminal encryption/decryption security for a cryptographic engine or processor.
Conventional wireline or wireless telecommunications are susceptible to interception and theft of the data being transmitted. In order to prevent the theft of information in both wireless and wireline configurations, information is encrypted before it is transmitted from one terminal and decrypted when it is received at another terminal. Encryption/decryption of transmitted information provides additional security in a telecommunication such that if the information is intercepted by an unauthorized person, it is not readily understandable by that person. Decryption of stolen data may be very difficult or impossible with certain complex encryption algorithms.
Due to the sophisticated encryption algorithms that may be used, the performance of the cryptographic encryption/decryption units is adversely affected. In addition, present day cryptographic units may suffer failure and transmit unencrypted data which may seriously compromise the integrity of the secure telecommunication system.
Further, these cryptographic engines or processors typically have several different kinds of processors to perform various functions during the encryption or decryption. Detecting faults in this myriad of processors is difficult at best. Often times these processors are specifically allocated to perform specific functions in the encryption/decryption process.
It would be highly desirable to have a cryptographic logic unit with many flexibly driven processors and a fault detection arrangement for rapid detection of faults throughout a number of processors of a cryptographic logic arrangement and preventing the transmission of any unencrypted information.